This relates generally to the packaging of semiconductor devices.
FIGS. 1 and 2 depict a cross-section and a top view of typical semiconductor device packages. In FIG. 1, package 100 comprises a substrate 110 on which is mounted a semiconductor integrated circuit die 120 in a flip-chip configuration. Die 120 is mechanically and electrically connected to substrate 110 by an array 125 of solder balls or solder bumps located between the die and the substrate. In many embodiments, an underfill 127 is also used to secure the die to the substrate. A second array 130 of solder balls or solder bumps provides mechanical and electrical connection between the package substrate 110 and the next level of packaging to which package 100 is connected. Electrical connection between solder balls 130 and solder balls 125 is provided by vias 140 that extend vertically through substrate 110 and wiring traces or planes 145 that extend horizontally across the upper surface of substrate 110 and/or through substrate 110 in one or more layers.
As in many prior art packages, a lid 150 is used to enclose the die on the substrate. A stiffener 155 is located on the periphery 115 of the substrate between the lid and the substrate so as to reduce warpage of the substrate. Alternatively, the stiffener could be formed as part of the lid. Further details on various lid structures are set forth in U.S. Pat. No. 6,888,238 of Altera Corporation, which is incorporated herein in its entirety.
The switching of input/output (I/O) circuits and the power delivery system for the semiconductor integrated circuit require large amounts of transient electric current. The electric charge for this current is conventionally stored in decoupling capacitors connected between the power and ground lines connected to the integrated circuit. In some semiconductor packages, these capacitors are mounted on substrate 110 along the four sides of integrated circuit die 120. In the cross-section of FIG. 1, two of these capacitors are identified as elements 160.
FIG. 2 is a top view of a similar integrated circuit package 200 with its lid removed. Corresponding elements of package 200 have been given the same numbers as the corresponding elements of FIG. 1 incremented by 100. Package 200 comprises a substrate 210 on which is mounted a semiconductor integrated circuit die 220. Line 270 indicates the approximate point on the periphery 215 of substrate 210 where the inner edge of the stiffener/lid would contact the substrate. When the stiffener/lid is in place, the stiffener/lid preferably contacts the substrate over substantially the entire peripheral area between line 270 and the sides of the substrate. Substrate 210 is rectilinear having four sides with adjacent sides meeting at right angles. Die 220 is also rectilinear having four sides with adjacent sides meeting at right angles. Illustratively, as shown in FIG. 2, both the substrate and the die are approximately square and the die is mounted so that it is centered on the substrate with the sides of the die parallel (and perpendicular) to the sides of the substrate. In other embodiments, the substrate and/or the die may be rectangular with two parallel sides that are appreciably different in length from the other two parallel sides. When the die is mounted on the substrate in a flip-chip configuration, the solder balls or solder bumps (not shown in FIG. 2) are typically arranged in a rectilinear array of rows and columns of solder balls or solder bumps parallel to the sides of die 220. Similarly, the solder balls or solder bumps (not shown in FIG. 2) that connect the package to other packaging levels are arranged in a rectilinear array of rows and columns parallel to the sides of substrate 210.
Decoupling capacitors may be connected between the power and ground lines connected to integrated circuit die 220. As in the case of capacitors 160 of FIG. 1, these capacitors may be mounted on substrate 210 between integrated circuit die 220 and the stiffener/lid. These capacitors are not shown in FIG. 2 to avoid undue complexity in the drawing.
Wiring traces 245 extend horizontally across and/or through substrate 210 to connect integrated circuit die 220 to the solder balls or solder bumps that connect the package to other packaging levels. Wiring traces or planes 245 also extend across and/or through substrate 210 to connect the decoupling capacitors (not shown) between power and ground lines. As shown in FIG. 2, the distribution of wiring traces varies along the periphery of the die and the periphery of the substrate. In particular, the distribution is quite sparse in the four corners 280 of the substrate defined by extending the sides of the die until they intersect the sides of the substrate and is much denser in the four mid-sections 285 between corners 280 and die 220. This variation in distribution is the source of significant inefficiencies in the use of the limited space on the substrate. For example, in the case where the substrate and the die are both square and the side of the substrate is twice the length of the side of the die, the area of the substrate is four times the area of the die. One-quarter of the space on the substrate is covered by the die; one-quarter of the space is in the four corners 280; and one-half the space is in the four mid-sections 285 between the four corners and the die. Thus, one-third of the available space on the die is sparsely utilized.